
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux IS
  PORT(d0,d1,d2,d3:IN STD_LOGIC_VECTOR(3 downto 0);
       a0,a1,a2,e_l:IN STD_LOGIC;
       f:OUT STD_LOGIC_VECTOR(3 downto 0));
END mux;
ARCHITECTURE mux_1 OF mux IS
SIGNAL sel:STD_LOGIC_VECTOR(2 downto 0);
BEGIN
sel<=a2&a1&a0;
  PROCESS(d0,d1,d2,d3,sel,e_l)
    BEGIN
    IF e_l='1' THEN f<="ZZZZ";
    ELSIF sel="000" THEN f<=d0;
    ELSIF sel="001" THEN f<=d1;
    ELSIF sel="010" THEN f<=d2;
    ELSIF sel="011" THEN f<=d3;
    ELSE f<="ZZZZ";
    END IF; 
    END PROCESS;
END mux_1;